1. Maskable interrupt sources that cannot preempt the kernel code and are thus able to invoke operating system APIs from within their handlers.

2. Maskable interrupt sources with the ability to preempt the kernel code and thus have a lower latency and are less subject to jitter, see Response Time and Jitter.

3. All Interrupt Requests (IRQs) issued by I/O devices give rise to maskable interrupts.

4. Disabled. When the system is in this state both the maskable regular and fast interrupt sources are disabled.

5. Init. When the system is in this state all the maskable interrupt sources are disabled.

6. While transferring control to the proper segment, the processor clears the IF flag, thus disabling further maskable interrupts.