(1) Hardware architecture and critical path analysis are also introduced.

(2) Moreover, a high throughput hardware architecture is proposed to implement the SFSD algorithm.

(3) The realization principle, the hardware architecture and its operating results are introduced in the context.

(4) Its hardware architecture is a multiprocessor, consisting of one microcomputer and four TRANSPUTERs.

(5) The software and hardware architecture of the emergency and safeguard system for the launching site is established, including the data, function description and input and output of it.

(6) Hardware architecture of LCD spliter included two parts:SDI signal processing subsystem and network communication subsystem.

(7) The hardware architecture is made up of modular controller, modular exponentiation controller, data register, and modular multiplication operation units.

(8) Beginning with the hardware architecture of an analog integrated circuit test macro, a discussion is devoted to the methods of direct programming and list-directed programming.

(9) We propose an efficient hardware architecture for deblocking filter in H. 264 AVC.

(10) Different TTA hardware architecture can be simulated without modification of the simulator itself.

(11) Keep in mind that AO is an extra-cost licensable component, and only available on 3.8 firmware for XS40 and XI50 appliances built on the 9235 (9004) hardware architecture.

(12) This paper develops a priority queuing model of finite units. This model not only solves some problems in the design of hardware architecture, but also is useful in studying priority queuing...

(13) The whole structure of the hybrid test system is introduced, the hardware architecture and two kind of key technologies of the system are elaborated.

(14) It introduces the basic theory of modulation domain analysis module and the module's hardware architecture.

(15) This paper develops a priority queuing model of finite units. This model not only solves some problems in the design of hardware architecture, but also is useful in studying priority queuing of fi...

(16) Moreover, according to this enhanced algorithm, the author designs hardware architecture of the decoder based on the pipelined technique and gives the timing diagram.